The present invention relates to a non-volatile memory device and, more particularly, to a non-volatile memory device and a method to compensate for a threshold voltage shift.
Flash memory that is non-volatile is classified into NAND flash memory or NOR flash memory. NOR flash memory has a structure in which memory cells are independently connected to a bit line and a word line and has a good random access temporal characteristic, whereas NAND flash memory has a structure in which a plurality of memory cells are connected in series, requiring only one contact per cell string, and is good in terms of the level of integration. Accordingly, the NAND structure is generally used in high-integrated flash memory.
The well-known NAND flash memory device includes a memory cell array, a row decoder and a page buffer. The memory cell array consists of a plurality of word lines extending along the rows, a plurality of bit lines extending along the columns, and a plurality of cell strings corresponding to the bit lines.
In recent years, in order to further improve the level of integration in flash memory, active research has been done into a multi-bit cell capable of storing a plurality of data bits into one memory cell. This kind of the memory cell is generally referred to as a “Multi-Level Cell (MLC)”. A memory cell of a single bit is referred to as a “Single-Level Cell (SLC)”.
The NAND flash memory may have an error due to changed characteristics as it operates for a long time.
FIG. 1 illustrates cell distributions in a MLC with the changed threshold voltage.
Referring to FIG. 1, a MLC memory device that can store 2-bit data can have four cell states, which represents data [11], [10], [00] and [01]. The respective cells are distributed depending on a program voltage. A cell having the state [11] refers to a cell that has not been programmed, and a cell having the state [10] refers to a cell that has been programmed to have a threshold voltage slightly higher than a first program voltage PV1.
Furthermore, a cell having the state [00] has a threshold voltage slightly higher than a second program voltage PV2, and a cell having the state [01] has a threshold voltage slightly higher than a third program voltage PV3.
Furthermore, in order to read the respective cells, first to third read voltages R1 to R3 are applied to determine cell states, so that programmed data can be confirmed.
Meanwhile, in NAND flash memory, an operating voltage should be set in order to secure a retention characteristic. That is, the threshold voltage of cells can change as the memory device is operated for a long period of time and the same data is retained. Therefore, a method of reducing error by setting the voltage of a cell from the beginning and performing program and read operations based on the characteristics has been developed.
If the program and erase operations of the MLC memory device are repeated, electrons are trapped between oxide layers between the floating gate and the substrate of the memory cell, increasing trap charges. The trap charges are detrapped as time goes and temperature rises, reducing the threshold voltage of a programmed cell. Accordingly, a program voltage, is set higher than a read voltage by taking the reduction of the threshold voltage into consideration (It can be seen from FIG. 1 that the program voltage is set higher than the read voltage).
However, as the threshold voltage is shifted lower, the threshold voltage can become lower than the read voltage, resulting in read errors. A fail phenomenon occurring due to this problem is called “retention fail”. Therefore, in order to prevent a retention fail, the threshold voltage must be increased, which needs to increase a pass bias for turning on unselected cells.
The increase of the pass bias causes a phenomenon in which the threshold voltage of an erased cell of unselected cells is increased, so that the threshold voltage of an unselected cell is abnormally increased. This phenomenon leads to a fail when there is a subsequent read operation. This is called “read disturb fail” caused by a read disturb.
A shift in the threshold voltage, causing the retention fail and the read disturb fail, is indicated by the dotted lines of FIG. 1.